Monolithic focal-plane arrays for near-infrared imaging have been demonstrated by a team of researchers from the Advanced Technology Center for Photonics and Optoelectronic Materials at Princeton University (Princeton, NJ), Sensors Unlimited (Princeton, NJ), and the New Jersey Institute of Technology (Newark, NJ). The arrays consist of indium gallium arsenide (InGaAs) PIN diode photodetectors, each integrated with an indium phosphide (InP) junction field-effect transistor (JFET) that serves as a switching element for individual pixel addressing.
Arrays as large as 16 × 16 have been fabricated integrating 528 devices—256 detectors and 272 JFETs—with more than 99% usable individual device yield. Each detector has an integrated JFET, with 16 column-address JFETs adjacent to the contact pads.
The figure shows a smaller 8 × 8 array, with a similar arrangement. The gold contact pads across the top connect with the column-address JFETs (top row of rectangles outlined in black). Each of the 64-pixel photodiode sites (shown in blue) is integrally connected to the drain of a JFET, and each column of JFETs is tied to the drain of the corresponding column-address JFET. The gates of the JFETs in each row are connected in parallel, with each row addressed by a single edge-contact pad (left). By biasing the gates of a given row and the appropriate column JFET, a selected pixel’s detector is addressed. By scanning the rows and columns, “the incident light can be imaged without a need for a separate, externally bonded multiplexer,” notes Princeton University’s Stephen Forrest.
Leakage currents from an entire pixel column are summed at the output and thus limit the array dimensions and detection sensitivity. To minimize such drain and gate leakage, an “encapsulation” of the JFETs was devised, consisting of a p+ layer both under the InP n-channel and around its perimeter that enables the depletion region to pinch off the channel. This effectively cuts the switching voltage to half of that required by JFETs having a single-gate p-n junction. Also the lack of exposed p-n junctions eliminates surface leakage from the side walls of the JFETs, producing drain leakage currents as low as 90 pA, which, according to Forrest, is “a thousandfold improvement” over conventional JFETs.
Integrating the detectors and JFETs eliminates the need for flip-chip or wire bonding infrared photodetectors to silicon CMOS or CCD multiplexer readout arrays as is currently done. Such a monolithic arrangement improves performance by reducing parasitic losses and, with fewer individual integrated circuits needed and simpler manufacturing, has the potential of reducing costs.
Rick DeMeis | Associate Editor, Technology
Rick DeMeis was Associate Editor, Technology for Laser Focus World from March 1995 through March 1997.