Sloppy arithmetic could speed video-processing algorithms
Cambridge, MA--A computer chip that performs imprecise calculations could process image data thousands of times more efficiently than existing chips.
Image-processing chips that return imprecise answers would be much smaller than those in today's computers and would consume less power, allowing many more processors to fit on a chip. But the question is how useful those imprecise calculations would be. If early results of a research project at MIT are any indication, the answer is -- surprisingly useful.
Simulating sloppiness
In May 2010, Joseph Bates, an adjunct professor of computer science at Carnegie Mellon University (Pittsburg, PA), came to the Massachusetts Institute of Technology (MIT: Cambridge, MA) as a visiting professor to work with a group led by Deb Roy, a researcher at MIT's Media Lab, to determine whether video algorithms could be retooled to tolerate sloppy arithmetic. George Shaw, a graduate student in Roy's group, began by evaluating an algorithm, commonly used in object-recognition systems, that distinguishes foreground and background elements in frames of video.
To simulate the effects of a chip with imprecise arithmetic circuits, Shaw rewrote the algorithm so that the results of all its numerical calculations were either raised or lowered by a randomly generated factor of between 0% and 1%. Then he compared its performance to that of the standard implementation of the algorithm. "The difference between the low-precision and the standard arithmetic was trivial," Shaw says. "It was about 14 pixels out of a million, averaged over many, many frames of video."
Bates' chip design looks to be particularly compatible with image and video processing. Although he hasn't had the chip manufactured yet, Bates has used standard design software to verify that it will work as anticipated. Where current commercial computer chips often have four or even eight "cores," or separate processing units, Bates' chip has a thousand; since they don't have to provide perfectly precise results, they're much smaller than conventional cores.
But the chip has another notable idiosyncrasy. In most commercial chips, and even in many experimental chips with dozens of cores, any core can communicate with any other. But sending data across the breadth of a chip consumes much more time and energy than sending it locally. So in Bates' chip, each core can communicate only with its immediate neighbors. Any computation that runs on the chip has to be easily divided into subtasks whose results have consequences mainly for small clusters of related subtasks -- those running on the adjacent cores. Fortunately, video processing seems to fit the bill.
Bates stresses that his chip would work in conjunction with a standard processor, shouldering a few targeted but labor-intensive tasks.
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John Wallace | Senior Technical Editor (1998-2022)
John Wallace was with Laser Focus World for nearly 25 years, retiring in late June 2022. He obtained a bachelor's degree in mechanical engineering and physics at Rutgers University and a master's in optical engineering at the University of Rochester. Before becoming an editor, John worked as an engineer at RCA, Exxon, Eastman Kodak, and GCA Corporation.