The global semiconductor chip shortage has led to significant frustration as organizations across many industries have resorted to plan B. However, it has also prompted significant investment in research and development efforts necessary to find new solutions.
Case in point – IBM and Samsung Electronics are jointly announcing a breakthrough that defies conventional semiconductor design and aims to reduce the energy usage of chips by 85 percent or double performance compared to scaled finFET transistors.
Developed by a joint team of researchers at the Albany Nanotech Complex, IBM and Samsung's new VTFET design prototype successfully implements transistors built vertically on the surface of a chip. Because transistors have, until now, been built horizontally to lie flat upon the surface of a semiconductor, this allows an exponential number of transistors to exist on a chip and removes density and energy efficiency constraints.
“We see high bandwidth communication between chips as advanced interconnect becoming more important in the years to come. Lasers, photonics and optics will have a critical role to play in these innovations,” Huiming Bu - Vice President, Hybrid Cloud Technology Research & Albany Operation, IBM Research tells Laser Focus World. “These adjacent technologies have continued to play an increasing role in system integration, and it is anticipated they would bring complementary values in parallel along with transistor architecture innovations well into the future.”
The VTFET process addresses many barriers to performance and limitations to extend Moore’s Law as chip designers attempt to pack more transistors into a fixed space. It also influences the contact points for the transistors, allowing for greater current flow with less wasted energy. Overall, the new design aims to deliver a twotimesimprovement in performance or an 85 percent reduction in energy use as compared to scaled finFET alternatives.
According to the paper Bu and his associates wrote for IEDM, “At fixed footprint and aggressively scaled gate pitches, VTFET nanosheets can deliver increased device drive due to a combination of good electrostatics, low parasitic losses, and area savings from the use of zero diffusion breaks. VTFET Nanosheets can avoid Lateral FET scaling limits to deliver an enhanced operating voltage range. VTFET Nanosheets can also provide greater drive strength and flexibility compared to FinFETs and Nanowires. The intrinsic benefit of VTFET circuit capacitance reduction (~ 50%) over scaled Lateral FET has been demonstrated in hardware.”
“We believe the areas of EDA, inline metrology and process control (controlling physical parameters along the vertical Z direction in mass production) are areas of rich opportunities for VTFET adoption in the industry,” says Bu. “We are introducing this new device architecture at IEDM this year and hence not associating it to any specific technology node yet. Our intent is to introduce the VTFET architecture with its many advantages and unique features. The actual node adoption is aimed to be after Nanosheet Technology.”
Peter Fretty | Market Leader, Digital Infrastructure
Peter Fretty began his role as the Market Leader, Digital Infrastructure in September 2024. He also serves as Group Editorial Director for Laser Focus World and Vision Systems Design, and previously served as Editor in Chief of Laser Focus World from October 2021 to June 2023. Prior to that, he was Technology Editor for IndustryWeek for two years.
As a highly experienced journalist, he has regularly covered advances in manufacturing, information technology, and software. He has written thousands of feature articles, cover stories, and white papers for an assortment of trade journals, business publications, and consumer magazines.