ESI unveils ultra-thin-wafer dicer for advanced 3-D packaging applications

San Francisco, CA--At Semicon West (July 13 to 15, 2010), Electro Scientific Industries (Portland, OR) unveiled a new laser-based system for ultrathin-wafer dicing. The fully automated 9900 system for rapidly dicing ultrathin (less than 50 microns thickness) silicon wafers delivers high die-break strength (DBS).

"As higher levels of functionality are being incorporated into portable electronic devices, the wafers required for advanced packaging and 3-D integration applications are getting thinner and thinner," said Nick Konidaris, president and CEO of ESI. "Our customers are pushing the current limits of traditional wafer-dicing equipment and are demanding advanced technologies to improve yields and total cost of ownership."

3-D integration will be pivotal
Miniaturization and convergence are driving a significant increase in 3-D packaging technology. Semiconductor Equipment and Materials International (SEMI) reports that 3-D integration is anticipated to be pivotal for future growth of the semiconductor industry.¹

Ultrathin wafers are required to support advances in 3-D packaging, such as:

--stacked memory for high-density storage applications

--system-in-package (SiP), which combines stacked logic and memory

--through-silicon-via (TSV) interconnect applications

There are challenges with using mechanical technology for dicing ultrathin wafers due to cracking, chipping, and other yield and quality issues. The 9900 reliably yields die that can withstand the rigors of advanced packaging requirements, says ESI.

The 9900 enables full-cut dicing of ultrathin wafers and scribing logic or system-on-chip (SoC) wafers on die-attach films (DAFs) in one integrated system. Some wafers have delicate, brittle, low-k materials on the topmost layers of the wafer; cutting through this without damage is critical. The 9900 uses a proprietary laser and dry-etch process to maximize die strength. It also uses a laser with a 355-nm-wavelength output to the ultrathin-wafer surface. This enables manufacturers to minimize scribe-line widths and produce more die per wafer.

For more info, see www.esi.com.

REFERENCE:

1. "3-D Integration: A Progress Report," Semiconductor Equipment and Materials International (SEMI).