Based on laser-annealing technology developed at Stanford University (Stanford, CA) and Lawrence Livermore National Laboratory (Livermore, CA), engineers at Ultratech Stepper (San Jose, CA) have progressed to an alpha product level in a tool to fabricate significantly shallower and more abrupt transistor junctions than are currently available through rapid thermal processing (RTP).
Previously thought impractical for semiconductor-scale manufacturing applications, laser annealing is likely to take on a key role as the semiconductor industry proceeds toward sub-100-nm feature sizes, according to Somit Talwar, who described the technology in July at the Semicon West exhibition in San Francisco, CA (see figure).
"In the industry today, people are shrinking gate lengths, and at the same time they need to also make shallower and shallower source-drain junctions on either side of those gates," said Talwar, who is vice president for process development applications in the Verdant Technologies division of Ultratech, which is pursuing the laser-annealing development. "The numbers that are required at this point are in the 100- to 300-Å range."
As junctions get narrower, however, electrical resistance increases because RTP approaches physical limits in terms of charge carriers that can be injected and activated in the smaller space. RTP uses lamp sources to heat the silicon very quickly—on the order of seconds—to temperatures of about 1000°C, Talwar said. "In that short time at those temperatures, the dopant atoms are accelerated onto lattice sites. But there is a certain limit, called the solubility limit, as to how many of these atoms can be activated and can contribute to electrical conductivity."
In the new laser-annealing process, however, a solid-state laser source heats the silicon to its 1400°C melting point in depths ranging from 50 to 1000 Å. This allows for a uniform distribution of dopant within the junction, exceeding the RTP solubility limit and decreasing electrical resistance in the junctions by an order of magnitude.
"The other thing that is critical to device fabrication is that the junctions have to be more abrupt," Talwar said. "The transition from an n-type doped area to a p-type doped area has to be as narrow as possible, and with the laser-annealing technology it can be made almost atomically abrupt."
An old technology
Laser-annealing technology is about four decades old, but was generally considered to be incapable of handling the spatial nonuniformities on a semiconductor wafer full of varying device geometries. Ultratech acquired technology and a research team in 1994 from Lawrence Livermore Labs focused on developing a projection laser-anneal process. "Instead of having to expose complete dyes, we would introduce a lithography component, so we could in fact expose individual transistors," Talwar said. "That process involved exposing a mask to a very uniform illumination and then projecting the mask upon the wafer."
Ultratech decided in the near term to focus the process, originally developed in the Stanford University laboratory of Tom Sigmon, on the current market need for annealing. Technical details are considered proprietary, but the method basically involves shaping the output beam of a solid-state laser to provide uniform illumination for a step-and-repeat process.
"We take the pseudo-Gaussian beam that comes out of the laser and we shape it into a rectangle with extremely good uniformity throughout," Talwar said. "We then match the size of that beam to the size of the dye, and so we are exposing a single dye in a single shot. We pulse the laser. We expose a single dye. Then we move on to the next dye and expose that. So it is a step and repeat process, very much like a stepper."
A key aspect of achieving beam uniformity resides in the technology that enables the illumination source to compensate for the variations in surface absorption across different circuit features on a wafer. The current alpha device has beam sizes of the order of 1 ¥ 1 cm, but Talwar said the production model will handle dye sizes up to the current industry maximum of 26 ¥ 34 mm.
"To date, we have demonstrated transistors down to 30 nm using the technology, and at this point we are ready to demonstrate circuits as well," he said. Since 1994, Verdant, originally sponsored by Sematech and DARPA in addition to Ultratech, has had 25 patents issued and has applied for 40 more. "So the work we have done is in developing processes to integrate the laser-annealing technology into a complementary metal-oxide semiconductor process," Talwar said. The next steps will be to work with customers on demonstrating functioning circuits and on placing tools in the field.
"There was a commonly held perception that problems related to varying wafer surface geometries were impossible to solve," Talwar said. "At this point we have demonstrated enough results to show that these are solvable and that they have been solved with a couple of concepts. It's partly a function of the homogenizing optics, but mainly a function of the process integration tricks that we play."