Optical Compute Interconnect: Co-packaged optics for AI infrastructure

April 23, 2025

2:00 PM ET / 1:00 PM CT / 11:00 AM PT / 7:00 PM BST

Duration: 1 hour

Already registered? Click here to log in. 

Summary

Future scale-up fabrics for AI infrastructure will require exponential increases in I/O bandwidth and extended connectivity. Co-packaged optical I/O can support this bandwidth requirement with higher bandwidth density, improved energy efficiency, low latency, and longer reach.

This webinar session describes Silicon Photonics as an enabling technology for the bandwidth growth with increased component integration, proven field reliability, and scalable manufacturing processes. It also covers Intel’s 4 Tbps Optical Compute Interconnect (OCI) chiplet, based on Intel in-house Silicon Photonics technology and co-packaged with next-generation CPU/GPU or other SOCs, as well as the path to 32 Tbps chiplets and beyond. 

The OCI chiplet combines a single Silicon Photonics Integrated Circuit (PIC) with integrated on-chip lasers and optical amplifiers (SOA), with an electrical IC. At OFC 2024, Intel demonstrated our first OCI chiplet design co-packaged with a concept Intel CPU running an error-free CPU-to-CPU link over fiber.work, showcase benchmarks against classical HPC technologies, and demonstrate how this new approach can help organizations tackle compute-intensive problems.